An integrated memory device comprises a plurality of memory cells that are usually arranged in a matrix of electroconductive supply lines. The matrix of electroconductive supply lines is composed of column and row lines which are also referred to as word lines (WL) and bit lines (BL). The memory cells are each positioned at the crosspoints of the electroconductive supply lines that are connected with the memory cell via a top and a bottom electrode. To perform a change of the information content in a particular memory cell at the addressed crosspoint, or to recall the content of the memory cell, the corresponding word and bit lines are selected and impacted either with a write current or with a read current.
Different kinds of semiconductor memories are known, e.g., a RAM (Random Access Memory). A RAM memory device is a memory with optional access, i.e., data can be stored under a particular address and can be read out again under this address later. A particular kind of RAM semiconductor memories are DRAMs (Dynamic Random Access Memory) which comprise in general only one single, correspondingly controlled capacitive element per memory cell, e.g., a trench capacitor, with the capacity of which one bit each can be stored as charge.
The charge or the information stored, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, wherein the corresponding information content is written in the memory cell again or is refreshed, respectively. In contrast to DRAMs, no “refresh” has to be performed in the case of SRAMs (Static Random Access Memory) as long as the supply voltage is applied to the chip. In the case of non-volatile memory types such as EPROMs, EEPROMs, and flash memories, the stored data remain stored even if the supply voltage is switched off.
In the instant context, the term semiconductor memory device primarily designates semiconductor memory devices such as functional memory devices (PLAs, PALs, etc.) and table memory devices such as ROM or RAM semiconductor devices, e.g., SRAMs and DRAMs, but also logic semiconductor devices, i.e., integrated (analog or digital) computing circuits.
In semiconductor devices or memory chips, respectively, integrated circuits are established by numerous processes during the manufacturing, which are, for instance, in the case of logic semiconductor devices, capable of performing logic functions, i.e., of processing data in correspondence with predetermined operations, in particular pursuant to a programmed sequence. In a semiconductor memory device, e.g., a RAM semiconductor memory chip, a plurality of memory cells are integrated, in which, by selective applying of a voltage, electric charge can be stored or read out as an information unit (bit).
Usually, semiconductor devices are, in the course of the manufacturing process, in the semi-finished and/or finished state, prior to the incorporation in appropriate semiconductor modules, subject to extensive tests checking their functioning. By using appropriate test devices or analyzers, respectively, further tests may be performed after the incorporation of the semiconductor devices in the semiconductor modules (so-called module tests), so as to check the interaction of the individual semiconductor devices in the semiconductor module. Moreover, tests for analyzing defects may be required if a semiconductor module shows malfunctions after the assembly or during operation.
For the common manufacturing of a plurality of semiconductor devices, a so-called wafer (a thin disc manufactured of monocrystalline silicon) is used as a rule. For the structuring of the later circuits, the wafer is subject to a plurality of working processes, e.g., coating, exposure, etching, diffusion and implantation processes. After the termination of the working processes, the semiconductor devices are individualized by the wafer being sawn apart or scratched and broken, so that the individual semiconductor devices or chips are then available for further processing.
After the finishing of the semiconductor devices (i.e., after the performing of the above-mentioned wafer processing steps), the semiconductor devices are subject to test processes for checking their functioning at one or a plurality of (further) test stations. By means of appropriate test apparatuses, the devices—that are finished, but still positioned on the wafer—may also be tested in so-called disc tests. After the sawing apart (or the scratching and breaking, respectively) of the wafer, the devices—which are then available individually—are molded in a plastics mass and may subsequently be subject to further test processes at one or a plurality of test stations.
During the manufacturing of a semiconductor device, a silicon substrate is consequently manufactured first of all in so-called front end processes (FE processes), the silicon substrate comprising the desired memory cells or integrated circuits, respectively. After the finishing of the silicon substrates or chips, respectively, and their individualization, the electrical connections (e.g., contact pads) of the chips are connected (e.g., bonded) via electrical connecting lines (bond wires) with a contact frame so as to enable the electrical contacting of the silicon substrate with the periphery via external contacts (e.g., pins).
Subsequently, the chips connected with the contact frame are, as a rule, molded in a plastics package along with the contact frame, so that a packed semiconductor device is generated. A plurality of such semiconductor devices may then be composed to form a semiconductor module. Alternatively, it is also possible that a number of semiconductor devices is composed to form a semiconductor module even prior to the molding in separate plastics packages and is molded together in a common package subsequently only. The processes following the individualization of the semiconductor memory devices are referred to as back end processes (BE processes).
During the manufacturing of memory devices, diverse test steps are consequently performed in the manufacturing stages of the front end (FE), the back end (BE), during burn-in (BI), and at semiconductor memory modules. Some of these test methods serve to repair a memory device that is not fully operable, or to check it in conformity with specifications at a certain rate action. In the following, a way of processing that is common for most semiconductor memory products will be described, by means of which the disadvantages of the presently used redundancy repair concept of prior art is illustrated.
In the manufacturing stage of the front end, the memory device or memory chips on the wafer are tested exactly parallel and with a low access rate. In so doing, it is determined, in particular with DRAM memory devices, which of the memory cells has a sufficient margin or rate action, respectively, with respect to the retention requirements, and which memory cells may have to and can be replaced by redundant cells. If all and any defective memory cells can be masked out by an exchange with redundant word lines (WL) or bit lines (BL), a repairable memory device (repairable chip) is available.
The test process in the FE manufacturing stage comprises the testing in the so-called pre-fuse and post-fuse test step, in which defective column select lines (CSL) and word lines (WL) are detected before or after the repair is performed by means of fusing. The test process is, as a rule, performed at least at a particular test temperature, preferably at a high temperature HT, and optionally additionally also at a low temperature LT. The column select lines are control lines leading to a group of particular sense amplifiers (SA) that are selected during a row selection by means of the y-address of a memory cell. In the memory device, so-called redundant column select lines (RCSL) are provided which may be used in exchange for defective CSLs.
The redundancy information of each memory device or chip on the wafer collected in the pre-fuse test are subsequently burnt in irreversibly in a fuse process (by e-fuse or laser fuse), and the wafer is tested with respect to a successively performed repair. At this stage, both repaired and non-repairable chips are available on the wafer. Non-repairable chips are chips whose available redundancy is not sufficient to produce a fully operable and specification-consistent memory device with a defined memory size.
The chips or memory devices that have been tested and found to be fully operable (FE-pass-parts) are usually picked from the wafer and supplied to the back end manufacturing stage so as to mold them in a package. The packed semiconductor devices or memory chips are then stressed, burnt in and tested at high voltages and temperatures in a so-called burn-in process. Subsequently, the semiconductor devices are tested for their rate performance in the BE test at low and at high temperature (LT and HT). The memory devices that have been found to be operable in the BE test (BE-pass-parts) are provided for the construction of memory modules, wherein between 4 and 36 memory devices per module are used and tested again to sort out defective modules being the result of soldering. A defective module may, for instance, be produced by soldering degradation, which is caused by a reduction in quality due to the temperature-induced ageing of the chip during soldering.
Each test step is, as a rule, based on a so-called test severity, i.e. a specified functionality rate action exceeding the chip specification, for which any electric circuit or any memory cell field (array) of the DRAM memory device is examined with regard to particular causes of defect. Due to the adjustment and guaranty of this test severity, each test step entails a certain loss of yield which can continuously be optimized in the course of series-production readiness by means of test and process optimization. Although exclusively pass-parts are used in the last manufacturing step of the module construction, hard (retention) single cell defects occur due to soldering degradation, which may make the entire module fail in particular in the case of high temperature operation. Here it is, as a rule, the matter of few, frequently only one single, defective memory cell in the memory device.
The object of the so-called single bit repair is to eliminate such defects of single memory cells (single cell defects) in the memory device, which have occurred after the repair performed in the front end manufacturing stage. This is, for instance, done by providing a supplementary repair possibility on the component or module level of the memory device. It is presupposed that the single cells of the semiconductor memory which are provided for repair are adapted to be integrated as easily as possible and have already been subject to the necessary burn-in stress or do not require same. The (redundant) single cells of the semiconductor memory which are provided for repair must further be tested with respect to all test requirements (FE/BI/BE) in correspondence with the memory cells to be exchanged, or must already fulfill or be able to guarantee same.
The elimination of single cell defects on the module level is of great interest in particular in the case of memory devices with high memory density since the probability of a module failure increases with the number of memory devices contained, or with the chip number and with the memory density per chip, respectively. Nevertheless, the possibility of single memory cell repair, also of single components, is of advantage in particular in BI test or in BE test. During the burn-in test, retention defects that have been found at high temperature can be eliminated in that single cell defects are removed in a so-called BE cold test at low temperature or in a so-called BE hot test at high temperature. This way, the total BE-yield, i.e. the yield of functionally tested memory devices after the BE test can be improved.
A known possibility of repairing defective memory cells consists in providing DRAM memory cells for redundancy so as to use them in the case of a single bit repair and to thus increase the yield e.g. on the module level. This proceeding, however, entails the problems that redundant elements for the repair of single memory cell defects (single bit repair or single bit redundancy, SBR) or of a bit group still have to be available for a single access. Moreover, the knowledge of the test quality of the still available redundancy alone at the time of FE fusing is not sufficient to use the redundancy memory cells in later test steps, for instance, after the BI or the BE test. A replacement of defective memory cells by memory cells that have not been tested sufficiently severely would mean a generation of semiconductor memory devices or modules with a lower quality standard vis-à-vis non-repaired memory devices. Thus, the use of a non-tested redundancy with lower test severity would involve a potential failure risk. An additional testing of the repaired memory devices in the BI or the BE is not desirable for cost reasons.
The quality of free redundancies has to be known at any time of a test sequence without them having to be established anew later or having to be tested separately, since this would increase the test time. In the case of the BI, this could also result in an overstressing of the memory areas that have already been stressed. The redundancy elements must be accessible or addressable, respectively, so that they are also examinable. The redundancy memory cells must be tested or stressed along with the regular memory cells and possibly also be deactivated if a defect in the redundancy is detected.
For these and other reasons, there is a need for the present invention.